As hand-held portable electronic devices such as cellular phones and palm computers are becoming more prevalent, conservation of chip space is an important consideration for designing IC (integrated circuit) packages to be used in such hand-held portable devices. A technique for conserving chip space is the use of a multichip IC (integrated circuit) package having a plurality of IC (integrated circuit) dies that are stacked.
Referring to FIG. 1, a top IC (integrated circuit) die 102 is stacked on top of a bottom IC die 104. The top IC die 102 has a plurality of bonding pads including a first bonding pad 112, a second bonding pad 114, a third bonding pad 116, a fourth bonding pad 118, a fifth bonding pad 120, and a sixth bonding pad 122 for providing connection to nodes of the integrated circuit of the top IC die 102. The bottom IC die 104 also has a plurality of bonding pads including a first bonding pad 132, a second bonding pad 134, a third bonding pad 136, a fourth bonding pad 138, a fifth bonding pad 140, and a sixth bonding pad 142 for providing connection to nodes of the integrated circuit of the bottom IC die 104. IC dies typically have more numerous bonding pads, but six bonding pads are shown for the top IC die 102 and the bottom IC die 104 of FIG. 1 for clarity of illustration.
A first area of the top IC die 102 is smaller than a second area of the bottom IC die 104 such that the bonding pads of the bottom IC die 104 are exposed for providing connection to nodes of the integrated circuit of the bottom IC die 104. In addition, the top IC die 102 is disposed inward from any edge of the bottom IC die 104 such that a perimeter area 150 of the bottom IC die 104 is exposed outside the first area of the top IC die 102. The bonding pads of the bottom IC die 104 are disposed at the perimeter area 150 of the bottom IC die 104 such that the bonding pads of the bottom IC die 104 are exposed.
The top IC die 102 is attached to the bottom IC die 104 with a die attach material. Referring to FIG. 2, a cross sectional view of a multichip IC package 200 having the top IC die 102 stacked on the bottom IC die 104 across line A--A in FIG. 1 is shown. The bottom IC die 104 is attached to a support frame 202 of the multichip IC package 200 with a die attach material 204. The bottom IC die 104 typically has a topside passivation layer 206 for protecting integrated circuit structures fabricated on the bottom IC die 104. The top IC die 102 is attached to the bottom IC die 104 with a die attach material 208. The top IC die 102 also typically has a topside passivation layer 210 for protecting integrated circuit structures fabricated on the top IC die 102.
A first conductive ball 212 is bonded to the second bonding pad 114 of the top IC die 102 for providing connection between the second bonding pad 114 and a lead of the multichip IC package 200. A second conductive ball 214 is bonded to the fifth bonding pad 120 of the top IC die 102 for providing connection between the fifth bonding pad 114 and a lead of the multichip IC package 200. A third conductive ball 216 is bonded to the second bonding pad 134 of the bottom IC die 104 for providing connection between the second bonding pad 134 and a lead of the multichip IC package 200. A fourth conductive ball 218 is bonded to the fifth bonding pad 140 of the bottom IC die 104 for providing connection between the fifth bonding pad 140 and a lead of the multichip IC package 200.
The multichip IC package 200 includes a plurality of ball leads including a first ball lead 222, a second ball lead 224, and a third ball lead 226 that are each coupled to a respective bonding pad of the top IC die 102 or the bottom IC die 104. IC packages typically have more numerous leads in an array of leads, but three ball leads of one row in an array of ball leads are shown for the IC package 200 of FIG. 2 for clarity of illustration. Elements having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function. The first area of the top IC die 102 and the perimeter area 150 of the bottom IC die 104 are covered with a plastic material 230 of the multichip IC package 200. Such multichip IC package structures are known to one of ordinary skill in the art of IC package manufacture.
During manufacture of IC packages, the IC packages are tested for proper functionality of the integrated circuits of the IC dies within the IC packages. When an IC package fails testing by exhibiting improper functionality, the cause of such failure is determined through "fault isolation" techniques as known to one of ordinary skill in the art of IC package manufacture. One such fault isolation technique is the use of "photon emission microscopy" which measures photon emission from the surface of an IC die. For measurement of photon emission from an area of the IC die in this fault isolation technique, the area of the IC die is exposed.
For the multichip IC package 200 of FIGS. 1 and 2, the top IC die 102 should be removed for use of "photon emission microscopy" on areas of the bottom IC die 104 that are initially covered by the top IC die 102. Referring to FIGS. 2 and 3, for separation of the top IC die 102 from the bottom IC die 104, the die attach material 208 between the top IC die 102 and the bottom IC die 104 is etched. In the prior art, the outside edge of the top IC die 102 is exposed to an etching solution. For example, the die attach material 208 may be comprised of liquid bismaleimide resin and polytetra-fluoroethylene (PTFE) fillers, as known to one of ordinary skill in the art of IC package manufacture. In that case, the etching solution for dissolving such a die attach material may be comprised of nitric acid (HNO.sub.3).
Referring to FIG. 3, when only the outside edge of the top IC die 102 is exposed to the etching solution, the contact area of the etching solution to the die attach material 208 between the top IC die 102 and the bottom IC die 104 (as illustrated by the arrows in FIG. 3) is small. Elements having the same reference number in FIGS. 1, 2, and 3 refer to elements having similar structure and function. Consequently, the time period for separation of the top IC die 102 from the bottom IC die 104 may be approximately 3 to 4 hours when the top IC die 102 has dimensions of approximately 0.29 inches by 0.27 inches for example. When the top IC die 102 and the bottom IC die 104 are exposed to the etching solution for such a long time period, the bonding pads of the IC dies 102 and 104 may be undesirably etched and destroyed.
However, interconnect of the bottom IC die 104 should be preserved for proper fault isolation testing of the bottom IC die 104.